課程大綱

課程資訊
學年期 Semester	1142	課程代碼 Course Code	ET3806301
課程名稱 Course Title	數位邏輯設計實習 Lab. of Digital Logic Design
學分數 Credits	1	選必修 Required/Elective	必修 /半學年
上課時間教室 Time/Location	M8(T2-511) M9(T2-511) M10(T2-511)
先修課程 Prerequisite(s)
授課教師 Lecturer	林敬舜 Ching-Shun Lin
專業核心能力 Core Professional Competencies

以下課程內容資料由授課教師提供
課程相關網址 Course Website	http://https://www.et.ntust.edu.tw/et/faculty.php?user=chingshl
課程宗旨 Objective of The Course	1. Introduction to TTL series IC and basic electronic devices. 2. Using basic devices for digital design: Oscilloscope, Function generator, Multi-meter, Logic analyzer and Power supply etc. 3. Introduction to basic tools for digital design: MAX+PLUS II, Quartus II, KeilC and ModelSim etc.. 4. Using ABEL to design digital circuit application for PALs. 5. Using Verilog HDL to design digital circuit application for CPLD/FPGA. 6.Using Microcontroller to design digital circuit application.
課程大綱 Outline of Lectures	• Binary number systems, number representations, and codes • Boolean algebra Boolean functions • Logic gates and circuits • Logic simplification using Boolean algebra and Karnaugh maps • Combinational logic design and building blocks • Synchronous sequential logic design and state machines • Latches, flip-flops, registers and counters • Programmable logic • Memory basic • Verilog programming
教科書 Textbook	1. Ming-Bo Lin, Digital Logic Design: With An Introduction to Verilog HDL, W. W. Norton, 2016. 2. Ming-Bo Lin, Digital Systems Design and Practice: Using Verilog HDL and FPGAs, CreateSpace Independent Publishing Platform, 2015. 3. Ming-Bo Lin, A Tutorial on FPGA-Based System Design Using Verilog HDL: Intel/Altera Quartus Version: Part I: An Entry-Level Tutorial, W. W. Norton, 2018. 4. M. Moris Mano and Michael D. Ciletti, Digital Design, Global Ed., Pearson, 2019.
參考書目 References	1. David Harris and Sarah Harris, Digital Design and Computer Architecture, 2nd Ed., Morgan Kaufmann, 2012. 2. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Ed., McGraw Hill, 2013. 3. Frank Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd Ed., John Wiley & Sons Inc, 2010.
修課學生須知 Notice of course enrollment	Tips for success in this class: • Familiarity with programming, such as the C language, is a plus. • Don’t miss class. • Read in advance. • Start homework early. • Don’t ignore the homework, and quizzes. • Ask questions. • Don’t arrive late for class.
評量方式 Grading	Operational exercises: 80 % Group discussion: 10 %, Attendance and Participation: 10 %
備註說明 Note	Teaching assistant is available.